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NOIL1SN3000A
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the ROT. See ROT_timer (b0000001 / d1) on page 21.
The default timing is in reduced ROT mode, so there is
no reduction in dynamic range.
Ds_en, bit<3> . Bit to enable dual slope operation.
Enabling this mode allows to enlarge optical dynamic
? Sel_pre_width, bit<5:4> . Setting these two bits allows
changing the width of the sel_pre pulse that is used to
precharge all column lines at the start of every ROT.
Changing these bits does not change the total ROT
length.
range.
Table 16. SEQUENCER REGISTER
Value
Powerdown, bit <0>
0
1
On startup
Reset_n_seq, bit<1>
0
1
On startup
Red_ROT, bit<2>
0
1
On startup
Ds_en, bit<3>
0
1
On startup
Sel_pre_width, bit<5:4>
00
01
10
11
On startup
ROT_timer (b0000001 / d1)
Effect
Normal operation
Image core in power down
0
Sequencer kept in reset
Normal operation
1
Long ROT mode
Reduced ROT mode
1
Disable dual slope operation
Enable dual slope operation
0
Sel_pre is 1 sensor clock period long (4 master clocks)
Sel_pre is 2 sensor clock periods long (8 master clocks)
Sel_pre is 3 sensor clock periods long (12 master clocks)
Same effect as ‘10’ setting
00
The ROT_timer register controls the length of the ROT.
The ROT length, in number of sensor clock periods, is
expressed by the formula: ROT length = ROT_timer + 2.
Table 17. ROT TIMER REGISTER
The relation between the row overhead time and the ROT
pin is described in the section ROT Pin on page 39. Bits
<7:5> are ignored.
Value Bit<4:0>
00000
xxxxx
On startup
Effect
ROT length is 35 sensor clocks, 140 master clocks.
ROT length is <N+2> sensor clocks (<N+2>*4 master clocks) where N is the register value
00111 (9 sensor clocks)
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